A chip-size package (CSP) refers to an ultra small package whose smallness and thinness are rendered close to those of an LSI chip to a possible degree. A wafer level chip size package (WLCSP) is known as an ultra small package which is fabricated by means of connecting individual LSIs of a wafer and corresponding electrodes and molding them with resin before the wafer is diced into the individual LSIs (separation); i.e., an ultra small package fabricated through direct packaging on a wafer (see Non-patent Document 1). In Patent Document 1, a double side electrode package which enables different similar packages to be disposed above and below the package in a stacked condition is disclosed as such a wafer level chip size package.
FIG. 16 shows a conventional double side electrode package disclosed in Patent Document 1. A multilayer wiring section is formed on the front face of a semiconductor substrate on which circuit elements are formed. In a stage of forming this multilayer wiring section, holes are formed in the semiconductor substrate, and through electrodes to be connected to the multilayer wiring section are formed in the holes. A back face insulation layer is formed on the back face of the semiconductor substrate such that tip ends of the through electrodes are exposed. Furthermore, post electrodes are connected to the uppermost wiring layer of the multilayer wiring section, and the post electrodes are covered with a front face insulation layer.
Subsequently, on the front face side, bump electrodes are formed on the tip ends of the post electrodes exposed from the front face insulation layer, and, on the back face side, bump electrodes are formed on the tip ends of the through electrodes exposed from the back face insulation layer.
In such a chip-size double side electrode package, both the upper and lower faces are covered with respective insulation layers. This configuration facilitates tests, and allows other packages having similar structures to be freely combined and disposed above and below the chip-size double side electrode package. The area of a completed double side electrode package is small; i.e., completely equal to that of the original chip. In addition, since mounting such a package on a substrate is easy, the package is suitable for high density mounting. Because of this feature, employment of such a double side electrode package in products which is small in mounting space, such as cellular phones and digital cameras, has been spreading.
In general, a semiconductor manufacturing process is divided into a former stage for fabricating an LSI and a latter stage for packaging the LSI. There are a few manufacturers that specialize in the latter stage but can cover the former stage. Manufacture of a conventional wafer level chip size package (WLCSP) requires a process of performing rewiring, post electrode plating, etc. on a wafer; that is, requires facilities similar to those used in the former stage, and cannot be performed by use of only conventional facilities for the latter stage. Therefore, it has not been easy to provide bump electrodes for external connection at positions different from those of the tip ends of post electrodes exposed to the surface of an insulation layer.